CoaXPress 2.1 IP Core
Host & Device · 1× / 2× / 4× lanes · AXI ready
A lane-scalable CoaXPress implementation with a single code base for both Host (frame grabber) and Device (camera) personalities, switchable at build time. Clean AXI interfaces, deterministic lane bonding, and a full BFM-driven verification suite.
ZCU106 · KCU116 · Aper-Oculus carrier — build scripts and constraints ready to run, with working camera and host example builds.
| Quick reference | |
|---|---|
| Per-lane rate | CXP-12 · 12.5 Gb/s |
| Lane modes | 1× / 2× / 4× |
| Aggregate | to 50 Gb/s (4×) |
| Personalities | Host · Device |
Table 1 — Key parameters. Full electrical characteristics under Specifications.
CXP Host & Device
Single code base supports both Host (frame grabber) and Device (camera) configurations with build-time switchable top-levels sharing the sublayers.
1× / 2× / 4× lanes
Scales from single-lane CXP-12 to quad-lane aggregation with lane bonding, alignment, and deterministic skew compensation.
AXI-Stream ready
Image and control paths expose clean AXI4-Stream / AXI4-Lite interfaces for DMA engines like XDMA or LitePCIe.
Production proven
Delivered and tested on Xilinx ZCU106, KCU116, and the Aper-Oculus carrier with working camera/host reference designs.
Documentation
Ready to integrate CoaXPress?
Ship faster with a verified, lane-scalable IP core and working designs for ZCU106, KCU116, and Aper-Oculus.