CoaXPress IP Core
Host & Device • 1× / 2× / 4× lanes • AXI Ready
A synthesizable, lane-scalable CXP2.0 implementation with clean AXI interfaces, deterministic timing, and a complete verification environment built on SystemVerilog Bus Functional Models (BFMs).
ZCU106 · KCU116 · Aper-Oculus carrier — build scripts and constraints ready to run.
FPGA‑Focused CoaXPress
Host and Device Configurations with lane‑bonded throughput up to 4× CXP‑12. Clean AXI interfaces, deterministic timing, and plug‑and‑play DMA integration.
CXP Host & Device
Single code base supports both Host (frame grabber) and Device (camera) Configurations with build-time switchable top-levels.
1× / 2× / 4× Lanes
Scales from single-lane CXP-12 to quad-lane aggregations. Includes lane bonding, alignment, and deterministic skew compensation.
AXI-Stream Ready
Image and control paths expose clean AXI4-Stream/AXI4-Lite interfaces for DMA engines like XDMA or LitePCIe.
Production Proven
Delivered and tested on Xilinx ZCU106, KCU116, and our Aper-Oculus carrier with working camera/host reference designs.
Why this IP
Throughput
Aggregate up to 50 Gbps with low latency and alignment across lanes.
Determinism
Cycle‑accurate state machines and synchronizers for reproducible behavior.
Modularity
Composable subcores: PHY shim, link, control, and video packing layers.
Ready to integrate CoaXPress?
Ship faster with a verified, lane‑scalable IP core and working designs for ZCU106, KCU116, and Aper‑Oculus.