SLVS‑EC IP Core
Baud 3 • 1× / 2× / 4× / 8× lanes • AXI Ready
A lane‑scalable SLVS‑EC receiver/transmitter core designed for high‑speed Sony sensors. Clean AXI interfaces, deterministic alignment, and a full SystemVerilog BFM‑driven verification suite. Reference bridges to PCIe and CoaXPress are included.
ZCU106 · KCU116 · Aper‑Oculus carrier — build scripts and constraints ready to run.
SLVS‑EC for High‑Speed Sensors
Baud‑3 capable SLVS‑EC IP with lane bonding up to 8 lanes. Clean AXI interfaces and ready‑made bridges to PCIe and CoaXPress accelerate your bring‑up.
1× / 2× / 4× / 8× Lanes
Configurable lane count with deterministic lane bonding, alignment FIFOs, and skew compensation across all modes.
Baud 3 (5 Gbps) Per Lane
High-speed operation validated in hardware at Baud 3 with clean clocking and robust reset/bring-up sequences.
Bridges to PCIe & CoaXPress
Reference pipelines included: SLVS‑EC → PCIe DMA and SLVS‑EC → CoaXPress, enabling capture or conversion designs.
Sensor‑Proven
Validated with Sony IMX547, IMX530, and IMX421 on Xilinx ZCU106, KCU116, and the Aper‑Oculus carrier.
Why this IP
Throughput
Up to ~40 Gbps aggregate with deterministic alignment across lanes.
Low‑Jitter Timing
Careful CDC and recovered‑clock handling for stable capture.
Modularity
PHY shim, link decode, packing, and control layers are cleanly separated.
Ready to integrate SLVS‑EC?
Ship faster with a Baud‑3 capable, lane‑scalable IP core and working designs for ZCU106, KCU116, and Aper‑Oculus.