SLVS-EC IP Core
Baud 3 · 1× / 2× / 4× / 8× lanes · AXI ready
A lane-scalable SLVS-EC receiver/transmitter core designed for high-speed Sony sensors. Clean AXI interfaces, deterministic alignment, and a full SystemVerilog BFM-driven verification suite. Reference bridges to PCIe and CoaXPress are included.
ZCU106 · KCU116 · Aper-Oculus carrier — build scripts and constraints ready to run.
| Quick reference | |
|---|---|
| Per-lane rate | Baud 3 · 5 Gb/s |
| Lane modes | 1× / 2× / 4× / 8× |
| Working bridges | PCIe · CXP |
| Sensors verified | IMX547 · 530 · 421 |
Table 1 — Key parameters. Full electrical characteristics under Specifications.
1× / 2× / 4× / 8× lanes
Configurable lane count with deterministic lane bonding, alignment FIFOs, and skew compensation across all modes.
Baud 3 — 5 Gb/s per lane
High-speed operation validated in hardware at Baud 3 with clean clocking and robust reset and bring-up sequences.
Bridges to PCIe & CoaXPress
Reference pipelines included: SLVS-EC → PCIe DMA and SLVS-EC → CoaXPress, enabling capture or conversion designs.
Sensor-proven
Validated with Sony IMX547, IMX530, and IMX421 on Xilinx ZCU106, KCU116, and the Aper-Oculus carrier.
Documentation
Ready to integrate SLVS-EC?
Ship faster with a Baud-3 capable, lane-scalable core and working designs for ZCU106, KCU116, and Aper-Oculus.