ApotheoTech · Orlando, FL

FPGA IP cores and hardware for high‑speed imaging.

Production CoaXPress 2.1, SLVS‑EC, NVMe, and 12G‑SDI cores for AMD/Xilinx platforms, with the evaluation hardware and engineering services to get them into your product.

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Fig. 1 — Live capture demonstration, ApotheoTech bench

Product line

Boards & IP cores

Aper-Oculus
BOARD · AT-CAR-K26-01

Aper-Oculus

Kria K26 carrier with SLVS-EC sensor interface and FMC expansion.

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CoaXPress FMC
BOARD · AT-FMC-CXP-01

CoaXPress FMC

CXP 2.1 host/device evaluation to 12.5 Gb/s on a single lane.

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SLVS-EC RX
IP CORE · IP-SLVSEC-RX

SLVS-EC RX

Baud 3, 1×–8× lanes, sensor-proven with IMX547 / 530 / 421.

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CoaXPress 2.1 Host / Device
IP CORE · IP-CXP-21

CoaXPress 2.1 Host / Device

Full-protocol CXP-1 through CXP-12 with GenICam path.

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NVMe
IP CORE · IP-NVME-HOST

NVMe

Direct-to-drive capture, no CPU in the datapath. PCIe Gen3.

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GPIO FMC
BOARD · AT-FMC-GPIO-01

GPIO FMC

RPi-compatible header and M.2 PCIe for fast prototyping.

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Aper-Oculus
BOARD · AT-CAR-K26-01

Aper-Oculus

Kria K26 carrier with SLVS-EC sensor interface and FMC expansion.

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01 · Hardware

Development platforms

Carrier boards and FMC cards designed alongside the IP, so evaluation starts on hardware that is already proven with the cores.

AvailableAT-CAR-K26-01

Aper‑Oculus

Kria K26 SOM carrier board with integrated SLVS‑EC sensor interface and FMC expansion. The reference platform for the SLVS‑EC RX core.

SOMAMD Kria K26
Sensor interfaceSLVS-EC
ExpansionFMC
PurchaseTechnical details
Aper-Oculus carrier board

CoaXPress FMC

Available
AT-FMC-CXP-01

Single-lane CXP 2.1 host/device evaluation card. Pairs with the CXP IP cores for a bench-ready bring-up.

Lanes1× TX/RX
Line rateto 12.5 Gb/s
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GPIO FMC

Available
AT-FMC-GPIO-01

Prototyping card with Raspberry Pi-compatible header and M.2 PCIe slot for storage or expansion.

HeaderRPi 40-pin
ExpansionM.2 PCIe
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SDI FMC

Coming soon
AT-FMC-SDI-01

Multi-rate SDI interface card for broadcast and professional video. Companion to the 12G-SDI IP core.

Rates3G / 6G / 12G
ApplicationBroadcast
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02 · IP Cores

Licensed IP portfolio

Every core ships with an example design, simulation models, and documentation. Perpetual licenses with annual maintenance.

CoaXPress 2.1 Host / Device

Full-protocol CXP 2.1 implementation, host and device sides, with reference designs, simulation models, and GenICam integration path.

ProtocolCXP 2.1
Line rateCXP-1 to CXP-12
DeliverablesNetlist + example design
ExamplesLicensing

SLVS-EC RX

Receiver core for Sony SLVS-EC image sensors. Deployed on Kria SOM and UltraScale+ targets, shipping in the Aper-Oculus platform.

StandardSLVS-EC
LanesConfigurable
DeliverablesNetlist + example design
ExamplesLicensing

NVMe

Direct-to-drive NVMe engine for sustained high-bandwidth capture, no CPU in the datapath. Proven in a 4K high-frame-rate recording pipeline.

InterfacePCIe Gen3
Use caseSustained capture
DeliverablesNetlist + example design
ExamplesLicensing
In development03 · Next

A high‑speed camera platform is coming.

4K capture at high frame rates with direct‑to‑NVMe recording, live preview, and playback, built on the same IP cores available for licensing today.

Get notified
High-speed camera platform
04 · Delivered work

Proven on real programs

DeliveredCase study

VCU300X, 8‑channel SDI conversion

Solo development of an 8× SDI 12G/6G/3G to On Board Computer conversion system with dual TV and audio channel processing and a custom PCIe DMA engine, from architecture through deployment.

Read the case study
ScopeDelivered
SDI channels8× 12G/6G/3G
DatapathCustom PCIe DMA
DriverCustom V4L2
IntegrationDesign to deployment
05 · Services

Engineering services

Available for programs that need specialized FPGA and high‑speed hardware expertise.

FPGA Development

Custom RTL, high-speed datapaths, and DSP on AMD/Xilinx platforms from 7-series through Versal.

High-Speed Interfaces

SLVS-EC, CoaXPress, and SDI bring-up, including transceiver tuning and protocol debug.

PCIe & DMA

Custom DMA engines and high-bandwidth transfer architectures, hardware through driver.

Linux Drivers

Kernel drivers, V4L2 capture pipelines, and userspace libraries matched to the hardware.

System Integration

Concept to deployment: PCB, firmware, gateware, and software delivered as one working system.

Feasibility & Consultation

Proof-of-concept builds and architecture reviews before you commit a program to silicon.

Discuss your project

Start a conversation.

IP licensing, hardware orders, or a program that needs an engineer who has shipped this class of system before.

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