ApotheoTech is an engineering company in Orlando, Florida. We design imaging systems end to end: the sensor board, the FPGA design behind it and the driver that hands frames to your software.
The hard bugs in a camera sit between the board, the FPGA and the driver. ApotheoTech takes all three on a project, so a fault can be followed from one into the next.
Sensor board
Processing board
We design the camera around your sensor and your data rate: the sensor board, the processing board, the FPGA design and the host software, delivered as one working system.
We write RTL from the specification for AMD FPGAs: sensor receivers, camera links, storage, and the transceiver work underneath them.
We write kernel drivers that make custom hardware show up as a standard device, so your software team keeps the tools it already uses.
Also available on their own: high-speed PCB design, Jetson camera integration and embedded firmware.
Stage 1 of 6: sensor readout
Receives Sony SLVS-EC image sensors at Baud 3, including the IMX530, IMX547 and IMX421. It runs on GTH, GTY and GTP transceivers, or on HP I/O when the transceivers are already in use. With AXI4-Stream out it uses 1,433 LUTs, 2,835 registers and 4 block RAMs.
ApotheoTech wrote the FPGA gateware, the PCIe DMA engine, the Linux driver and a sample application for an eight-input SDI capture card, as one project.
A frame grabber, designed here, that receives a four-lane CXP-12 camera and delivers it to the host over PCIe.
Customer names are kept off this site.
The interface work is also sold as products. The cores are licensed as encrypted netlists and quoted per project. The boards ship from the store. All products, in full
Both ends of the link from one code base, for frame grabbers and for cameras.
CXP-12, 12.5 Gb/s per lane, 1 to 4 lanes
A receiver for Sony SLVS-EC sensors, on transceivers or on HP I/O when the transceivers are taken.
Baud 3, 1 to 8 lanes, GTH, GTY, GTP or HP I/O
Records an AXI4-Stream straight to an M.2 SSD, with no processor in the write path.
PCIe Gen3 and Gen4, x1, x2 and x4
A PCIe Gen4 MAC for LitePCIe is in development. Details
Kria K26 carrier with an SLVS-EC sensor connector and an FMC slot. The reference platform for all three cores.
Made to order
One CoaXPress lane, Host or Device, with the cable equalizer and driver on board.
In stock
A Raspberry Pi 40-pin header, two PMOD ports and an M.2 slot on one FMC card.
In stock
Multi-rate SDI up to 12G, with reference designs and an SDI camera demo.
Waitlist
Step 1
The sensor or interface, the data rate, the FPGA or host you have in mind, and where the project stands today. A paragraph is enough to start.
Step 2
We reply within one business day. The scope names what will be built, what it will be tested on and what you receive at the end.
Step 3
A fixed price when the deliverable can be defined up front, or time and materials while the requirements are still moving.
Step 4
Design, simulation and bring-up on real hardware. The FPGA, the board and the driver are debugged together.
Updated November 2026
Write-ups from bring-ups and debug sessions
Say what the sensor or interface is, how fast the data moves and what it has to reach. We reply within one business day.
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