Products

CoaXPress 2.1 cores for AMD FPGAs with GTH or GTY transceivers. The Host goes in a frame grabber and the Device goes in a camera. Both come from one code base, and both build for 1, 2 or 4 lanes of CXP-12, which is 12.5 Gb/s per lane.

Video moves on AXI4-Stream and control on AXI4-Lite. The Host reads and writes camera registers over the control channel. The Device carries the register bank and serves the GenICam XML. Hardware triggers are generated on the Host and decoded on the Device.

License either end, or license both and test them against each other on one board. Lane count is a build option, and a single-lane license costs less when 12.5 Gb/s is enough.

A receiver for Sony SLVS-EC image sensors on AMD FPGAs. It comes with two PHY options: the GTH, GTY or GTP transceivers, or plain HP I/O. Both run at Baud 3, and both are validated with the IMX530, IMX547 and IMX421.

Each lane has its own PHY front end. The lanes are aligned and deskewed, packet headers are decoded with ECC, payloads are checked by CRC, and lines are rebuilt across lanes. Video leaves on AXI4-Stream, with control, status and per-lane error counters on AXI4-Lite.

The HP I/O option is for UltraScale and UltraScale+ designs whose transceivers are already spent on PCIe, CoaXPress or Ethernet. Lane count is a build option from 1 to 8. On the Aper-Oculus the core runs an IMX530 on 2 lanes at 3840 x 2160 and 30 fps.

An NVMe host controller for AMD FPGAs that writes an AXI4-Stream straight to an M.2 SSD. No CPU and no operating system sit in the write path.

The core runs on its own PCIe root-port stack. The transaction and data link layers were written in house, so it is not tied to one hard block: it runs over AMD's PG239 soft PHY or the PG213 hard block. A queue engine builds PRP lists for long sequential writes and applies backpressure to the source when the drive stalls.

Choose the generation and the link width that fit the drive, the data rate and the transceivers you have left. A Gen4 x4 link carries up to 7.88 GB/s before protocol overhead, and a Gen3 x1 link 0.98 GB/s.

The PCIe MAC that sits under the NVMe host core, packaged for LitePCIe. It drives AMD's PG239 PHY on UltraScale+ GTH and GTY transceivers and presents the interface LitePCIe expects from a hard PHY.

An existing LitePCIe design can therefore move to Gen4 without the hard PCIe block, and the rest of the design does not change. The transaction and data link layers are the ones that already carry the NVMe host core in hardware.

This core is in development. Early access customers help set the first supported configurations.