8‑channel 12G‑SDI capture card for PCIe.
Eight SDI inputs at 12G, 6G, or 3G into a PCIe Gen3 x8 host link. The FPGA gateware, the Linux V4L2 driver, and the sample application were all written by one engineer, and the client had working code in twelve weeks.
The whole stack, one engineer
Not a gateware contract with the driver thrown over a wall. The FPGA design, the kernel driver, and a working application on top were delivered together, by the same person, against the same deadline.
FPGA gateware
- Eight SDI receiver front ends with 12G/6G/3G rate autodetect
- Embedded audio extraction and processing pipeline
- PCIe Gen3 x8 DMA engine across ten channels
- Dynamic memory management sized to worst-case burst
- PCIe flash controller for in-field firmware update
- Real-time status and error monitoring
Linux driver stack
- V4L2 capture driver presenting all channels as standard devices
- PCIe driver integration and device enumeration
- DMA buffer management with zero-copy paths to userspace
- Flash update utilities
- Userspace libraries for application integration
Sample application
- Working reference application against the delivered driver
- Demonstrated simultaneous capture across all inputs
- Gave the client a running starting point, not just an API
- Documentation and handover
Where a project like this usually goes wrong
None of the three pieces is exotic on its own. The combination, on this schedule, is the part worth paying for.
Three disciplines, one deadline
A 12G-SDI front end, a PCIe DMA engine, a V4L2 kernel driver, and an application on top are normally four different people on three different teams. Most of the schedule in that arrangement is spent at the interfaces between them, deciding whose bug it is.
No slack in the bandwidth budget
Eight SDI inputs feeding a PCIe Gen3 x8 link leaves very little headroom. The DMA scheduling, the buffer sizing, and the memory subsystem had to be designed against worst case simultaneously, not tuned afterwards.
Timeline against convention
A system of this shape is typically quoted at six to twelve months with a full team. This one was specified, built, integrated, and deployed in twelve weeks, because hardware and software progressed in parallel rather than in sequence.
What the system does
Eight independent SDI receivers, each detecting its own incoming rate, feeding a shared DMA engine over PCIe Gen3 x8. Embedded audio is extracted alongside the video rather than handled downstream.
Firmware is updatable in the field over PCIe, so the card does not have to come out of the chassis to be revised.
- SDI inputs
- 8 channels, 12G / 6G / 3G with rate autodetect
- Audio
- Embedded audio extraction and processing
- Host interface
- PCIe Gen3 x8, custom DMA engine, 10 channels
- Throughput
- 64 Gbps aggregate
- Driver
- Custom V4L2 capture driver, Linux
- Firmware update
- PCIe flash controller, in-field capable
- Delivery
- 12 weeks, architecture through commissioning
Twelve weeks, start to commissioned
Hardware and software ran in parallel throughout. The driver was being written against the gateware while the gateware was still being built, which is only possible when the same person owns both sides of the interface.
System architecture and requirements
Week 1Complete technical specification and development roadmap.
FPGA core development
Weeks 2 to 7Verified design covering full SDI and audio processing.
Linux driver and software stack
Weeks 8 to 10Complete Linux stack, V4L2 compliant.
Integration and deployment
Weeks 11 to 12Working system delivered and commissioned.
Have something with this shape?
High-speed capture, a host interface that has to keep up, and a driver stack underneath it. If your project spans gateware, kernel, and application, that span is the reason to talk.