Products / Software

Software for the host side

Linux drivers, image processing and a camera control application, each developed and tested with the ApotheoTech cores and boards.

  1. Sony sensorIMX530, IMX547, IMX421
  2. SLVS-EC RXGTH, GTY, GTP or HP I/O
  3. FPGA ISPBinning, ROI crop
  4. CXP DeviceCXP-12, 1 to 4 lanes
  5. Coax, CXP-12
  6. CXP HostAXI4-Stream out
  7. NVMe hostGen3 / Gen4, x1 to x4
    SSDM.2 NVMe drive
    PCIe to hostLitePCIe DMAV4L2 driverZero-copy, VSYNC awareCUDA ISPJetson AGX Orin
In development

V4L2 frame grabber drivers

One Linux driver for every LitePCIe capture card, on x86 and Jetson AGX Orin. Frames arrive at /dev/video0, so standard V4L2 tools and applications work unchanged.

  • vb2 dma-contig buffers, one per frame, zero copy to userspace
  • VSYNC-aware DMA: an early VSYNC moves to the next buffer, so frames never tear
  • Interrupt-driven link events: lock, loss of lock, uplink and errors
  • Shared across CoaXPress, SDI and future capture cards

Sold separately. Reference designs include a basic frame grabber without VSYNC alignment.

Frames moving from the FPGA through DMA buffers to a video device
In development

Camera ISP, CPU and CUDA

Demosaic through color and tone, written on the CPU first and then ported to CUDA on the Jetson AGX Orin. The target is graded, cinema-quality footage from machine vision sensors.

  • 8 to 16-bit Bayer input, MSB aligned
  • CPU reference pipeline for bit-exact checking
  • CUDA pipeline on Jetson AGX Orin
  • Tuning live from the camera GUI

Availability and licensing to be announced.

Illustration of ISP tuning in CamView: a test chart split down the middle, raw Bayer data on the left and the finished color picture on the right, with controls for demosaic, color and tone beside it
Illustration. Screenshots from the running application will replace it.
In development

FPGA ISP stages

Image processing stages that run in fabric between the sensor receiver and the link out, each configured over AXI4-Lite.

  • Horizontal binning
  • Region-of-interest crop
  • More stages to follow

Availability and licensing to be announced.

Sensor receiverLink out
  1. Horizontal binning
  2. Region-of-interest crop
  3. More stages
    to follow
AXI4-Lite: configures each stage
FPGA ISP stages. Solid blocks are in development now.
Running on hardware

CamView

A camera viewer and control application for CoaXPress hosts. It discovers, negotiates and locks the link, reads the camera's GenICam XML, builds its controls from it, then streams.

  • Camera features parsed straight from the XML, no GenICam runtime binaries
  • Features the camera does not support are greyed out
  • Live camera and ISP tuning, savable settings, fullscreen view
  • CoaXPress today; other transports later

Used in the CoaXPress Host demos.

Illustration of CamView: a live test chart on the left, the link's steps from discovered to streaming along the top, and one control for each feature in the camera's XML on the right, two of them greyed out as not supported
Illustration. Screenshots from the running application will replace it.

Custom drivers for your hardware

Custom V4L2 and PCIe drivers are part of the Linux driver service.

Linux driver servicesContact