FPGA Design Services
Contract RTL design and custom IP core development on AMD/Xilinx platforms, by the engineer who writes the cores.
Most FPGA contract work stops at integrating vendor IP. The interface cores on this site were written from scratch: CoaXPress 2.1 Host and Device, SLVS-EC RX, and NVMe. That means when a link will not train, or a transceiver will not lock, or a datasheet and a sensor disagree, the debugging happens at the protocol level rather than against a black box.
Engagements run from a bounded core integration through full design ownership: architecture, RTL, constraints, timing closure, simulation, and hardware bring-up on real silicon.
Custom IP and RTL
- Protocol cores written from specification, not adapted from reference designs
- CoaXPress 2.1 Host and Device, SLVS-EC RX, NVMe, 12G-SDI, Ethernet
- AXI4 / AXI4-Stream / AXI4-Lite interconnect and register maps
- GenICam-compliant camera control and XML description
- IP packaging and encryption for redistribution to your customers
High-speed serial
- GTH, GTY, and GTP transceiver configuration and DRP runtime reconfiguration
- Multi-lane alignment, link training, and rate negotiation
- Clock domain crossing and elastic buffering across recovered clocks
- Equalisation and eye-margin debug against real cable and backplane loss
Platforms and closure
- Kria K26 and K24 SOM, Zynq UltraScale+ MPSoC, Artix and Kintex
- Vivado from block design through timing closure and bitstream
- Constraint authoring: timing, placement, and I/O planning
- Simulation and verification benches, ILA-based hardware debug
Built, shipped, and debugged on real hardware
CoaXPress 2.1 Host and Device
A full CXP-12 implementation covering both link directions, with GenICam control, packet layer, and cable discovery. Shipping as a licensed core.
SLVS-EC RX
Sony SLVS-EC receiver handling multi-lane alignment and sensor-specific framing, targeting sensors where no vendor IP exists.
NVMe Host
An NVMe host controller for direct-to-storage capture, so high-rate sensor data lands on an SSD without a CPU in the path.
Scope that fits the problem
- Fixed-scope core integration and bring-up on your hardware
- Custom protocol core developed to your specification
- Design rescue: timing closure, link stability, or interface debug on an existing project
- Ongoing retained design capacity
Related work on this site
These are shipping products from the same bench. They are the clearest evidence of what the service delivers.
Discuss a project